Generally, in a DRAM (dynamic random access memory) memory cell array, as is shown in FIG. 11, a single memory cell MCij is arranged (connected) at the intersection point of the word line WLi that is provided in each row and the bit line BLj that is provided in each column. Each memory cell MCij is constructed of a single N-type MOS transistor Qij and a single cell capacitor Cij. Each word line WLi is connected to the word line driver WDi of each row, and each bit line BLj is connected to the sense amplifier SAj of each column. The construction of one portion of the memory cell array shown in FIG. 11 is shown simplified for the purpose of facilitating the explanation.
When writing to the memory cell MCij is conducted, the word line driver WDi turns on the transistor Qij by driving to the potential to the H level or activating the word line WLi, and simultaneously with this, the sense amplifier SAj places the potential of the bit line BLj at the H level VDL or the L level VSS in response to the write information ("1" or "0"). In this way, the cell capacitor Cij receives a charging voltage of VDL or VSS. After this, the word line driver WDi lowers the word line WLi to the L level VSS, and the transistor Qij is turned OFF. As a result of this, a charging voltage or a charge of "1" VDL or "0" VSS is maintained at the cell capacitor Cij.
When reading is conducted, the sense amplifier SAj temporarily precharges the bit line BLj beforehand to a fixed potential (generally, VDL/2), and the word line driver WDi turns the transistor Qij ON by activating or driving the word line WLi to an H level. In this way, the bit line BLj and the cell capacitor Cij are short-circuited, and the potential on the bit line BLJ is slightly changed from the precharge level in response to the accumulated charge of the cell capacitor Cij. The stored information of the memory cell MCij is recognized by means of the sense amplifier SAj detecting and amplifying this slight potential change on this bit line BLj.
Incidentally, with a large-scale DRAM such as, for example, the 64 Mb class, a memory cell array construction is used wherein the memory cell array within a single chip is divided into multiple blocks or submatrices, and the memory cell array within the respective submatrices are divided into multiple memory cell array units.
Within each submatrix, a fixed number of memory cell array units are placed at a fixed spacing and arranged in a matrix form. Also, as is shown in FIG. 12, adjacent to each memory cell array unit MA, for example, the collector circuits (word line driver banks) WDB, WDB are arranged relatively opposite on both the left and right sides, and the collector circuits (sense amplifier banks) SAB, SAB are arranged relatively opposite on both the upper and lower sides. Also, the cross areas CR are provided diagonally next to each memory cell array unit MA.
In FIG. 12, for purposes of simplification of the illustration, only the layout of the memory cell array unit MA of four units (2 vertical.times.2 horizontal) that are relatively adjacent and their peripheral circuits is shown.
Within the memory cell array unit MA, the prescribed number (rows) of bit line pairs BL/BL- and the prescribed number (columns) of word lines WL are arranged in a matrix form, and memory cells MC are connected at the intersection point of each bit line BL (also each complementary bit line BL- and each word line. Each word line WL within the array MA is connected to the corresponding word line driver WD that is arranged in the word line driver banks WDB, WDB for both the left and right sides. Also, each bit line/each complementary bit line within the array MA is connected to the corresponding sense amplifier SA that is arranged in the sense amplifier banks SAB, SAB on both the upper and lower sides.
In each cross area CR are provided the drivers for the purpose of writing to the sense amplifiers SA within the connected sense amplifier banks SAB, and the drivers and the like (not illustrated) for the purpose of driving the word lines drivers WD within the connected word line driver banks WDB, and the like.
A typical partial cross-sectional view of the important sections is shown in FIG. 13 in regard to the line A--A' of FIG. 12. This cross-sectional construction shows the well construction in the vicinity of the boundary of the memory cell array unit MA and the sense amplifier bank SAB.
In this DRAM, a triple well construction is used, and an N-type deep (deep layer) well 102 is layered under the region for the memory cell array unit MA and the region for the word line driver bank WDB (not illustrated in FIG. 13). The area in which this N deep well 102 is distributed (hatching section) is shown in a planar view in FIG. 14.
In FIG. 13, the memory cell array unit MA is formed in the P well 104, which is the P-type region. In other words, each N-type MOS transistor and cell capacitor (not illustrated) that construct the prescribed number of memory cells that are contained in the unit memory cell array MA are formed in the surface and on the surface of the P well 104.
The sense amplifier bank SAB is constructed across the N well 106, which is the N-type region of the center section, and the pair of P wells 108, 110 that are on both sides of that. These wells 106, 108, 110 are formed without the interposition of a deep well on the main surface of the P-type silicon substrate 100. Among the elements that construct the circuit for the sense amplifier SA, the P-type MOS transistors are formed in the N-type well 106, and the N-type MOS transistors are formed in the P-type wells 108, 110.
The region PG used for well isolation that is made up of the N well 112 is arranged between the unit memory cell array MA and the sense amplifier bank SAB. The N deep well 102 that is arranged under the unit memory cell array MA and the word line driver bank WDB extends to under the N well 112 used for this well isolation.
In this type of construction, the back bias of the voltage VPP (for example, 3.8 V) is supplied to the N deep well 102 by means of the N well (not illustrated) of the word line driver bank WDB. Here, VPP is equivalent to the power supply voltage VPP used for the word line drive that is supplied to the P-type MOS transistor that is formed in the N well of the word line driver bank, and VPP is also applied as a back bias to the N well of the word line driver bank WDB.
A back bias of the voltage VBB (for example, -1.0 V) that is independent from the peripheral circuit section is supplied to the P well 104 of the unit memory cell array MA. Because the P well 104 of this array is electrically isolated from the P well of the peripheral circuit section by means of the well isolating region 112, the optimum back bias for the pause characteristics of the memory cell becomes selectable.
At the sense amplifier bank SAB, a back bias that is equal to the sensing drive voltage VDL (for example, 2.2 V) for the H level side is supplied to the N well 106 in which the P-type MOS transistors are provided, and a back bias that is equal to the sensing drive voltage VSS (for example, 0 V) for the L level side is supplied to the P wells 108, 110 in which the N-type MOS transistors are provided.
A back bias voltage VPP that is the same as that of the N deep well 102 is supplied to the N well 112 of the well isolation region PG.
The boundary section between the cross area CR, the unit memory cell array MA, and the word line driver bank WDM are also of the same cross-sectional construction as mentioned above, and the same type of back bias as mentioned above is supplied to each section.
In the DRAM construction used in the past such as mentioned above, the well isolation region PG is provided in the boundary sections of the unit memory cell array MA and the sense amplifier bank SAB, and the boundary section between the word line driver or bank WDM and the cross area CR, respectively. For example, when the sense amplifier bank SAB is designed to a width size of 40 .mu.m, a width of 7 .mu.m is selected for the well isolation regions PG. Therefore,. a space with a width of 14 .mu.m is taken up for both sides of the sense amplifier section. Because of this, the entire submatrix body, and by extension, the layout surface area of the entire chip, is made large.
This invention was made considering these problems, and its purpose is to offer a semiconductor device that realizes a reduction of the layout surface area by making unnecessary the regions used for well isolation such as mentioned above.